The UART is a type of a serial communication protocol which serves the purpose of full. The Verilog HDL code has been simulated in the ModelSim 10.1d. The block diagram for UART is as shown in the figure.1.
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Code DownloadVersion 1.0:Initial Public Release Features. VHDL source code of a Universal Asynchronous Receiver/Transmitter (UART) component. Full duplex. Configurable baud rate. Configurable data width. Configurable parity (even/odd/none).
Configurable oversampling rate for receive data. No flow controlIntroductionThis details a UART component for use in CPLDs and FPGAs, written in VHDL. The component was designed using Quartus II, version 13.1.0. Resource requirements depend on the implementation. Figure 1 illustrates a typical example of the UART integrated into a system.Figure 1. Example Implementation BackgroundA UART is a device used for asynchronous serial communication. It consists of two lines for data transmission, RX and TX, one in each direction.
Sometimes additional lines are included to implement flow control, most commonly RTS (Ready to Send) and CTS (Clear to Send). The transmission speed, data width, parity, and flow control are all configurable and must be set the same for both UART correspondents.Figure 2 show the data framing for a transmission. Absent communication, the line is held high to indicate that it and the transmitter are not damaged. A transaction begins with a low start bit.
The data word follows. Next comes an optional parity bit, which can be configured to even parity, odd parity, or no parity. Finally, a high stop bit ends the transaction.Figure 2. Data FramingThe communication can be simplex, half duplex, or full duplex.
In this component, the transmit and receive lines operate independently. While this makes the component inherently full duplex, it can also operate as either simplex or half duplex if controlled by the user logic to do so. Theory of Operation Generating Baud Rate and Oversampling Rate Clock EnablesThe baud rate is the transmission speed of the data in bits/second. The oversampling rate is the number of times the receive circuitry samples the receive input per baud period (i.e. Per data bit).This component achieves the baud rate and oversampling rate by generating clock enable pulses at those frequencies.
These signals are derived from the frequency of the system clock clk, which must be specified in the generic parameter clkfreq.A counter within the component generates a baud pulse that occurs at the baud rate. This periodic pulse enables the system clock to operate the transmit circuitry at the baud rate. There is a small error introduced each baud period, since the generated baud rate must be an integer multiple of the system clock.
However, this error will not exceed one period of the system clock.Similarly, another counter generates an oversampling pulse that occurs at a frequency = oversampling rate. baud rate.
This pulse enables the system clock to operate the receive circuitry at the oversampling rate. Note that this counter is also reset at each baud pulse, so that counting errors do not accumulate beyond one baud period. In this manner, the achieved baud rate of the receive circuitry is identical to the transmit circuitry baud rate. Transmit CircuitryWhen the txena input is asserted, the data on txdata is latched into an internal shift register. At this time, the parity bit is also calculated using XOR logic and latched into the same shift register, along with the start and stop bits. The baud pulse then periodically enables the system clock to shift out the register contents to the tx line at the baud rate.
The txbusy output indicates to the user logic when the transmission is complete and the circuitry is ready to accept new data to send. Receive CircuitryThe receive circuitry monitors the rx input on each oversampling pulse. If it detects a logic low, it starts counting and recognizes an incoming start bit once it detects a sufficient number of consecutive low inputs. At this point, it begins shifting the value of the rx line into a shift register at the baud rate, achieved by counting oversampling pulses.Once the entire data word is shifted into the register, the receive circuitry verifies the data parity using XOR logic. It then outputs the received data on the rxdata port and flags any error detected on the rxerror port.
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A high-to-low transition on the rxbusy port signifies to the user logic that new receive data is now available. Configuring the UARTThe UART is configured by setting the GENERIC parameters in the ENTITY. Table 1 describes the parameters.Table 1. Generic Parameter Descriptions. GenericData TypeDefaultDescriptionclkfreqinteger50000000Frequency of the system clock input (PORT clk) (Hertz)baudrateinteger19200Data link baud rate (bits/second)osrateinteger16Oversampling rate to find the center of receive bits (samples per baud period)dwidthinteger8Data width (bits)parityinteger10: no parity bit (parityeo is irrelevant) 1: include parity bitparityeostandard logic'0'0': even parity '1': odd parityPort DescriptionsTable 2 describes the UART’s ports.Table 2. Port Descriptions.
Random Access MemoryHere, the implementation of RAM (random access memory) is shown. The systemhas a data input bus (datain), a data output bus (dataout), an addressbus (addr), along with clock (clk) and write enable (wrena) pins. Whenwrena is given, at the next rising edge of clk the vector present atdatain stored in the position given by addr.
The capacity chosen for theRAM is 16 words of length 8 bits each. Notice that the code is totallygeneric. Simulation results from the circuit synthesizad with the VHDL codeare shown below. LIBRARY ieee;USE ieee.stdlogic1164.all;ENTITY ram ISGENERIC ( bits: INTEGER:= 8; - # of bits per wordwords: INTEGER:= 16); - # of words in the memoryPORT ( wrena, clk: IN STDLOGIC;addr: IN INTEGER RANGE 0 TO words-1;datain: IN STDLOGICVECTOR (bits-1 DOWNTO 0);dataout: OUT STDLOGICVECTOR (bits-1 DOWNTO 0));END ram;ARCHITECTURE ram OF ram ISTYPE vectorarray IS ARRAY (0 TO words-1) OFSTDLOGICVECTOR (bits-1 DOWNTO 0);SIGNAL memory: vectorarray;BEGINPROCESS (clk, wrena)BEGINIF (wrena='1') THENIF (clk'EVENT AND clk='1') THENmemory(addr).
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